View ADF4212BRU_4999398.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adf4210/adf4211/adf4212/adf4213 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual rf/if pll frequency synthesizers functional block diagram oscillator clock data le 24-bit data register if lock detect muxout adf4210/adf4211/ adf4212/adf4213 cp rf cp if phase comparator output mux 14-bit if r-counter ref in rf prescaler rf in phase comparator 14-bit rf r-counter 12-bit rf b-counter 6-bit rf a-counter v dd 1v dd 2v p 1v p 2 agnd rf dgnd rf dgnd if agnd if rf lock detect sdout dgnd if if prescaler if in 8-bit if a-counter charge pump if current setting reference rfcp3 rfcp2 rfcp1 r set fl o switch fl o if current setting ifcp3 ifcp2 ifcp1 reference charge pump r set 12-bit if b-counter features adf4210: 550 mhz/1.2 ghz adf4211: 550 mhz/2.0 ghz adf4212: 1.0 ghz/2.7 ghz adf4213: 1.0 ghz/3 ghz 2.7 v to 5.5 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable dual modulus prescaler rf and if: 8/9, 16/17, 32/33, 64/65 programmable charge pump currents 3-wire serial interface analog and digital lock detect fastlock mode power-down mode applications base stations for wireless radio (gsm, pcs, dcs, cdma, wcdma) wireless handsets (gsm, pcs, dcs, cdma, wcdma) wireless lans communications test equipment catv equipment general description the adf4210/adf4211/adf4212/adf4213 is a dual frequency synthesizer that can be used to implement local oscillators (lo) in the upconversion and downconversion sections of wireless receivers and transmitters. they can provide the lo for both the rf and if sections. they consist of a low-noise digital pfd (phase frequency detector), a precision charge pump, a pro- grammable reference divider, programmable a and b counters and a dual-modulus prescaler (p/p + 1). the a (6-bit) and b (12-bit) counters, in conjunction with the dual modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter), allows selectable refin frequencies at the pfd input. a complete pll (phase- locked loop) can be implemented if the synthesizer is used with an external loop ?ter and vco (voltage controlled oscillators). control of all the on- chip registers is via a sim ple 3-wire interface. the devices operate with a power supply ranging from 2.7 v to 5 v and can be powered down when not in use.
rev. a C2C adf4210/adf4211/adf4212/adf4213?pecifications 1 (v dd 1 = v dd 2 = 3 v 10%, 5 v 10%; v dd 1, v dd 2 v p 1, v p 2 6.0 v ; agnd rf = dgnd rf = agnd if = dg n d if = 0 v; r set = 2.7 k dbm to 50 ; t a = t min to t max unless otherwise noted.) p arameter b version b chips 2 unit test conditions/comments rf/if characteristics (3 v) rf input frequency (rf in ) see figure 3 for input circuit. adf4210 0.1/1.2 0.1/1.2 ghz min/max use a square wave for frequencies lower than f min . adf4211 0.1/2.0 0.1/2.0 ghz min/max adf4212 0.15/2.7 0.15/2.7 ghz min/max adf4213 0.2/3.0 0.2/3.0 ghz min/max rf input sensitivity ?0/0 ?0/0 dbm min/max if input frequency (if in ) adf4210 60/550 60/550 mhz min/max adf4211 60/550 60/550 mhz min/max adf4212 0.06/1.0 0.06/1.0 ghz min/max adf4213 0.06/1.0 0.06/1.0 ghz min/max if input sensitivity ?0/0 ?0/0 dbm min/max maximum allowable prescaler output frequency 3 165 165 mhz max rf/if characteristics (5 v) rf input frequency (rf in ) see figure 3 for input circuit. adf4210 0.18/1.2 0.18/1.2 ghz min/max use a square wave for frequencies lower than f min . adf4211 0.18/2.0 0.18/2.0 ghz min/max adf4212 0.2/2.3 0.2/2.3 ghz min/max adf4213 0.2/2.5 0.2/2.5 ghz min/max rf input sensitivity ?/0 ?/0 dbm min/max if input frequency (if in ) adf4210 100/550 100/550 mhz min/max adf4211 100/550 100/550 mhz min/max adf4212 0.1/1.0 0.1/1.0 ghz min/max adf4213 0.1/1.0 0.1/1.0 ghz min/max if input sensitivity ?/0 ?/0 dbm min/max maximum allowable prescaler output frequency 3 200 200 mhz max refin characteristics see figure 2 for input circuit. refin input frequency 0/115 0/115 mhz min/max for f < 5 mhz, use dc-coupled square wave (0 to v dd ). refin input sensitivity 4 ?/0 ?/0 dbm min/max ac-coupled. when dc-coupled, 0 to v dd max (cmos-compatible) refin input capacitance 10 10 pf max refin input current 100 100 a max phase detector phase detector frequency 5 55 55 mhz max charge pump i cp sink/source programmable: see table v high value 5 5 ma typ with r set = 2.7 k ? low value 625 625 a typ absolute accuracy 3 3 % typ with r set = 2.7 k ? r set range 1.5/5.6 1.5/5.6 k ? , min/max i cp three-state leakage current 1 1 na typ sink and source current matching 2 2 % typ 0.5 v v cp v p ?0.5 v i cp vs. v cp 2 2 % typ 0.5 v v cp v p ?0.5 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 0.8 dv dd 0.8 dv dd v min v inl , input low voltage 0.2 dv dd 0.2 dv dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage dv dd ?0.4 dv dd ?0.4 v min i oh = 500 a v ol , output low voltage 0.4 0.4 v max i ol = 500 a
rev. a C3C adf4210/adf4211/adf4212/adf4213 parameter b version b chips 2 unit test conditions/comments power supplies v dd 1 2.7/5.5 2.7/5.5 v min/v max v dd 2v dd 1v dd 1 v p v dd 1/6.0 v dd 1/6.0 v min/v max v dd 1, v dd 2 v dd 1, v dd 2 6.0 v i dd (rf + if) 6 adf4210 11.5 11.5 ma max 9.0 ma typical adf4211 15.0 15.0 ma max 11.0 ma typical adf4212 17.5 17.5 ma max 13.0 ma typical adf4213 20 20 ma max 15 ma typical i dd (rf only) adf4210 6.75 6.75 ma max 5.0 ma typical adf4211 10 10 ma max 7.0 ma typical adf4212 12.5 12.5 ma max 9.0 ma typical adf4213 15 15 ma max 11 ma typical i dd (if only) adf4210 5.5 5.5 ma max 4.5 ma typical adf4211 5.5 5.5 ma max 4.5 ma typical adf4212 5.5 5.5 ma max 4.5 ma typical adf4213 5.5 5.5 ma max 4.5 ma typical i p (i p 1 + i p 2) 1.0 1.0 ma max t a = 25 c, 0.55 ma typical low-power sleep mode 1 1 a typ noise characteristics adf4213 phase noise floor 7 ?71 ?71 dbc/hz typ @ 25 khz pfd frequency ?64 ?64 dbc/hz typ @ 200 khz pfd frequency phase noise performance 8 @ vco output adf4210/adf4211, if: 540 mhz output 9 ?1 ?1 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency adf4212/adf4213, if: 900 mhz output 10 ?9 ?9 dbc/hz typ see note 11 adf4210/adf4211, rf: 900 mhz output 10 ?9 ?9 dbc/hz typ see note 11 adf4212/adf4213, rf: 900 mhz output 10 ?1 ?1 dbc/hz typ see note 11 adf4211/adf4212, rf: 1750 mhz output 12 ?5 ?5 dbc/hz typ see note 11 adf4211/adf4212, rf: 1750 mhz output 13 ?7 ?7 dbc/hz typ @ 200 hz offset and 10 khz pfd frequency adf4212/adf4213, rf: 2400 mhz output 14 ?8 ?8 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency spurious signals adf4210/adf4211, if: 540 mhz output 9 ?8/?0 ?8/?0 db typ @ 200 khz/400 khz and 200 khz pfd frequency adf4212/adf4213, if: 900 mhz output 10 ?0/?4 ?0/?4 db typ see note 11 adf4210/adf4211, rf: 900 mhz output 10 ?0/?4 ?0/?4 db typ see note 11 adf4212/adf4213, rf: 900 mhz output 10 ?0/?4 ?0/?4 db typ see note 11 adf4211/adf4212, rf: 1750 mhz output 12 ?0/?2 ?0/?2 db typ see note 11 adf4211/adf4212, rf: 1750 mhz output 13 ?5/?0 ?5/?0 db typ @ 10 khz/20 khz and 10 khz pfd frequency adf4212/adf4213, rf: 2400 mhz output 14 ?0/?2 ?0/?2 db typ @ 200 khz/400 khz and 200 khz pfd frequency notes 1 operating temperature range is as follows: b version: ?0 c to +85 c. 2 the b chip speci?ations are given as typical values. 3 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the if/rf inp ut is divided down to a frequency that is less than this value. 4 v dd 1 = v dd 2 = 3 v; for v dd 1 = v dd 2 = 5 v, use cmos-compatible levels, t a = 25 c. 5 guaranteed by design. sample tested to ensure compliance. 6 v dd = 3 v; p = 16; rf in = 900 mhz; if in = 540 mhz, t a = 25 c. 7 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 logn (where n is the n divider value). see tpc 16. 8 the phase noise is measured with the eval-adf4210/adf4212/adf4213eb evaluation board and the hp8562e spectrum analyzer. the spe ctrum analyzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 9 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f if = 540 mhz; n = 2700; loop b/w = 20 khz. 10 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz. 11 same conditions as listed in note 10. 12 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 1750 mhz; n = 8750; loop b/w = 20 khz. 13 f refin = 10 mhz; f pfd = 10 khz; offset frequency = 200 hz; f rf = 1750 mhz; n = 175000; loop b/w = 1 khz. 14 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 1960 mhz; n = 9800; loop b/w = 20 khz. speci?ations subject to change without notice.
rev. a adf4210/adf4211/adf4212/adf4213 C4C db0 (lsb) (control bit c1) clock data le le db20 (msb) db19 db2 db1 (control bit c2) t 6 t 5 t 1 t 2 t 3 t 4 figure 1. timing diagram timing characteristics limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock set-up time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le set-up time t 6 20 ns min le pulsewidth notes guaranteed by design but not production tested. speci?ations subject to change without notice. (v dd 1 = v dd 2 = 3 v 10%, 5 v 10%; v dd 1, v dd 2 v p 1, v p 2 6 v 10%; agnd rf = dgnd rf = agnd if = dgnd if = 0 v; t a = t min to t max unless otherwise noted.) absolute maximum ratings 1, 2 (t a = 25 c unless otherwise noted) v dd 1 to gnd 3 . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v dd 1 to v dd 2 . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v v p 1, v p 2 to gnd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v p 1, v p 2 to v dd 1 . . . . . . . . . . . . . . . . . . . . ?.3 v to +5.5 v digital i/o voltage to gnd . . . . . . ?.3 v to dv dd + 0.3 v analog i/o voltage to gnd . . . . . . . . . ?.3 v to v p + 0.3 v ref in , rf in a, rf in b, if in a, if in b to gnd . . . . . . . . . . . . ?.3 v to vdd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c tssop ja thermal impedance . . . . . . . . . . . . . 150.4 c/w csp ja (paddle soldered) . . . . . . . . . . . . . . . . . . . 122 c/w csp ja (paddle not soldered) . . . . . . . . . . . . . . . . 216 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high-performance rf integrated circuit with an esd rating of < 2 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v. transistor count 11749 (cmos) and 522 (bipolar). ordering guide model temperature range package description package option * adf4210bru ?0 c to +85 c thin shrink small outline package (tssop) ru-20 adf4210bcp ?0 c to +85 c chip scale package cp-20 adf4211bru ?0 c to +85 c thin shrink small outline package (tssop) ru-20 adf4211bcp ?0 c to +85 c chip scale package cp-20 ADF4212BRU ?0 c to +85 c thin shrink small outline package (tssop) ru-20 adf4212bcp ?0 c to +85 c chip scale package cp-20 adf4213bru ?0 c to +85 c thin shrink small outline package (tssop) ru-20 adf4213bcp ?0 c to +85 c chip scale package cp-20 * contact the factory for chip availability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf4210/adf4211/adf4212/adf4213 features proprietary esd protection circuitry, per- manent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd prec autions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a adf4210/adf4211/adf4212/adf4213 C5C pin function descriptions pin number tssop mnemonic function 1v dd 1 power supply for the rf section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 1 should have a value of between 2.7 v and 5.5 v. v dd 1 must have the same potential as v dd 2. 2v p 1 power supply for the rf charge pump. this should be greater than or equal to v dd 1. in systems where v dd 1 is 3 v, it can be set to 6 v and used to drive a vco with a tuning range up to 6 v. 3cp rf output from the rf charge pump. this is normally connected to a loop ?ter which drives the input to an external vco. 4 dgnd rf ground pin for the rf digital circuitry. 5rf in input to the rf prescaler. this low level input signal is ac-coupled from the rf vco. 6 agnd rf ground pin for the rf analog circuitry. 7fl o rf/if fastlock mode. 8 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k ?. this input can be driven from a ttl or cmos crystal oscillator. 9 dgnd if digital ground for the if digital, interface and control circuitry. 10 muxout this multiplexer output allows either the if/rf lock detect, the scaled rf, scaled if or the scaled reference frequency to be accessed externally. 11 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 12 data serial data input. the serial data is loaded msb ?st with the two lsbs being the control bits. this input is a high impedance cmos input. 13 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 r set connecting a resistor between this pin and ground sets the maximum rf and if charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is i r cp max set = 13 5 . so, with r set = 2.7 k ? , i cp max = 5 ma for both the rf and if charge pumps. 15 agnd if ground pin for the if analog circuitry. 16 if in input to the rf prescaler. this low-level input signal is ac-coupled from the if vco. 17 dgnd if ground pin for the if digital, interface, and control circuitry. 18 cp if output from the if charge pump. this is normally connected to a loop lter which drives the input to an external vco. 19 v p 2 power supply for the if charge pump. this should be greater than or equal to v dd 2. in systems where v dd 2 is 3 v, it can be set to 6 v and used to drive a vco with a tuning range up to 6 v. 20 v dd 2 power supply for the if, digital and interface section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 2 should have a value of between 2.7 v and 5.5 v. v dd 2 must have the same potential as v dd 1. pin configurations tssop top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 data clk muxout dgnd rf rf in agnd rf dgnd if ref in fl o le r set agnd if v dd 1 v dd 2 v p 2 if in dgnd if cp if v p 1 cp rf adf4210/ adf4211/ adf4212/ adf4213 cp-20 1 2 3 4 5 agnd rf fl o cp rf rf in dgnd rf v dd 2 v p 2 cp if v p 1 v dd 1 20 19 18 17 16 15 14 13 12 11 dgnd if if in le r set agnd if 6 7 8 9 10 ref in dgnd if muxout data clk top view (not to scale) adf4210/ adf4211/ adf4212/ adf4213
rev. a adf4210/adf4211/adf4212/adf4213 C6C typical performance characteristics frequency s 11 real s 11 imag 50000000.0 150000000.0 250000000.0 350000000.0 450000000.0 550000000.0 650000000.0 750000000.0 850000000.0 950000000.0 1050000000.0 1150000000.0 1250000000.0 1350000000.0 1450000000.0 1550000000.0 1650000000.0 1750000000.0 1850000000.0 1950000000.0 2050000000.0 0.955683 0.956993 0.935463 0.919706 0.871631 0.838141 0.799005 0.749065 0.706770 0.671007 0.630673 0.584013 0.537311 0.505090 0.459446 0.381234 0.363150 0.330545 0.264232 0.242065 0.181238 ?.052267 ?.112191 ?.185212 ?.252576 ?.323799 ?.350455 ?.408344 ?.455840 ?.471011 ?.535268 ?.557699 ?.604256 ?.622297 ?.642019 ?.686409 ?.693908 ?.679602 ?.721812 ?.697386 ?.711716 ?.723232 2150000000.0 2250000000.0 2350000000.0 2450000000.0 2550000000.0 2650000000.0 2750000000.0 2850000000.0 2950000000.0 0.138086 0.102483 0.054916 0.018475 ?.019935 ?.054445 ?.083716 ?.129543 ?.154974 ?.699896 ?.704160 ?.696325 ?.669617 ?.668056 ?.666995 ?.634725 ?.615246 ?.610398 frequency s 11 real s 11 imag tpc 1. s-parameter data for the adf4213 rf input (up to 3.0 ghz) 2khz 1khz 900mhz +1khz +2khz v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 200khz loop b andwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 19 91.2dbc/hz reference level = 5.2dbm output power db 100 90 80 70 60 50 40 30 20 10 0 tpc 2. adf4213 phase noise (900 mhz, 200 khz, 20 khz) 10db/division r l = 40dbc/hz rms noise = 0.6522 100hz frequency offset from 900mhz carrier 1mhz 0.65 rms phase noise dbc/hz 90 80 70 60 50 40 100 110 120 130 140 1khz 10khz 100khz tpc 3. adf4213 integrated phase noise (900 mhz, 200 khz, 35 khz, typical lock time: 200 s) 0 rf input power dbm 30 20 10 0 t a = +25 c t a = 40 c 35 25 5 15 rf input frequency ghz v dd = 3v v p = 3v 123 t a = +85 c tpc 4. input sensitivity (adf4213) 10db/division r l = 40dbc/hz rms noise = 0.5421 100hz frequency offset from 900mhz carrier 1mhz 0.54 rms phase noise dbc/hz 90 80 70 60 50 40 100 110 120 130 140 1khz 10khz 100khz tpc 5. adf 4213 integrated phase noise (900 mhz, 200 khz, 20 khz, typical lock time: 400 s) 400khz 200khz 900mhz 200khz 400khz v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop b andwidth = 20khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 4.2 seconds averages = 20 91.0dbc/hz reference level = 5.7dbm output power db 100 90 80 70 60 50 40 30 20 10 0 tpc 6. adf4213 reference spurs (900 mhz, 200 khz, 20 khz)
rev. a adf4210/adf4211/adf4212/adf4213 C7C 400khz 200khz 900mhz +200khz +400khz v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 200khz loop b andwidth = 35khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 4.2 seconds averages = 25 reference level = 5.7dbm 90.5dbc/hz output power db 100 90 80 70 60 50 40 30 20 10 0 tpc 7. adf4213 reference spurs (900 mhz, 200 khz, 35 khz) 10db/division r l = 40dbc/hz rms noise = 1.6 100hz frequency offset from 1750mhz carrier 1mhz 1.6 rms phase noise dbc/hz 90 80 70 60 50 40 100 110 120 130 140 tpc 8. adf4213 integrated phase noise (1750 mhz, 30 khz, 3 khz) 2khz 1khz 3100mhz +1khz +2khz v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 1mhz loop b andwidth = 100khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 45 reference level = 4.2dbm 86.6dbc/hz output power db 100 90 80 70 60 50 40 30 20 10 0 tpc 9. adf4213 phase noise (2800 mhz, 1 mhz, 100 khz) 400hz 200hz 1750mhz +200hz +400hz v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 30khz loop b andwidth = 3khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 477ms averages = 10 reference level = 8.0dbm 75.2dbc/hz output power db 100 90 80 70 60 50 40 30 20 10 0 tpc 10. a df4213 phase noise (1750 mhz, 30 khz, 3 khz) 80khz 40khz 1750mhz +40khz +80khz v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 30khz loop b andwidth = 3khz res. bandwidth = 3hz video bandwidth = 3hz sweep = 255 seconds positive peak detect mode reference level = 5.7dbm 0 10 20 30 40 50 60 70 80 90 100 power output db 79.6dbc tpc 11. adf4213 reference spurs (1750 mhz, 30 khz, 3 khz) 10db/division r l = 40dbc/hz rms noise = 1.7 100hz frequency offset from 3100mhz carrier 1mhz 1.7 rms phase noise dbc/hz 90 80 70 60 50 40 100 110 120 130 140 tpc 12. adf4213 integrated phase noise (2800 mhz, 1 mhz, 100 khz)
rev. a adf4210/adf4211/adf4212/adf4213 C8C 2mhz 1mhz 3100mhz +1mhz +2mhz v dd = 3v, v p = 5v i cp = 5ma pfd f requency = 1mhz loop b andwidth = 100khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 13 seconds averages = 1 reference level = 17.2dbm 80.6dbc output power db 100 90 80 70 60 50 40 30 20 10 0 tpc 13. adf4213 reference spurs (2800 mhz, 1 mhz, 100 khz) temperature c 100 40 0 20 40 60 80 100 phase noise dbc/hz 70 80 90 60 20 v dd = 3v v p = 3v tpc 14. adf4213 phase noise vs. temperature (900 mhz, 200 khz, 20 khz) tuning voltage volts 5 0234 105 first reference spur dbc 75 85 95 5 1 v dd = 3v v p = 5v 65 35 45 55 15 25 tpc 15. adf4213 reference spurs (200 khz) vs. v tune (900 mhz, 200 khz, 20 khz) phase detector frequency khz 1 10000 100 1000 180 phase noise dbc/hz 140 150 160 170 120 130 10 v dd = 3v v p = 5v tpc 16. a df4213 phase noise (referred to cp output) vs. pfd frequency temperature c 100 40 0 20 40 60 80 100 first reference spur dbc 70 80 90 60 20 v dd = 3v v p = 5v tpc 17. adf4213 reference spurs vs. temperature (900 mhz, 200 khz, 20 khz) temperature c 100 40 0 20 40 60 80 100 phase noise dbc/hz 70 80 90 60 20 v dd = 3v v p = 5v tpc 18. adf4213 phase noise vs. temperature (836 mhz, 30 khz, 3 khz)
rev. a adf4210/adf4211/adf4212/adf4213 C9C temperature c 100 40 0 20 40 60 80 100 first reference spur dbc 70 80 90 60 20 v dd = 3v v p = 5v tpc 19. adf4213 reference spurs vs. temperature (836 mhz, 30 khz, 3 khz) circuit description reference input section the reference input stage is shown below in figure 2. sw1 and sw2 are normally-closed switches. sw3 is normally-open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. buffer to r counter ref in 100k nc sw2 sw3 no nc sw1 power-down control nc = no connect figure 2. reference input stage rf/if input stage the rf/if input stage is shown in figure 3. it is followed by a 2-stage limiting ampli er to generate the cml (current mode logic) clock levels needed for the prescaler. av dd agnd 2k 2k 1.6v bias generator rf in a rf in b figure 3. rf/if input stage prescaler (p/p + 1) the dual modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = pb + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf/if input stage and divides it down to a manageable frequency for the cmos a and b counters in the rf and if sections. the prescaler in both sections is programmable. it can be set in software to 8/9, 16/17, 32/33, or 64/65. see tables iv and vi. it is based on a syn- chronous 4/5 core. rf/if a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feed back counter. the counters are speci ed to work when the prescaler output is 200 mhz or less, when v dd = 5 v. typically, they will work with 250 mhz output from the prescaler. thus, with an rf input frequency of 2.5 ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: f vco = [( p b ) + a ] f refin / r f vco = output frequency of external voltage controlled oscillator (vco). p = preset modulus of dual modulus prescaler (8/9, 16/17, etc.). b = preset divide ratio of binary 13-bit counter (3 to 8191). a = preset divide ratio of binary 6-bit a counter (0 to 63). f refin = external reference frequency oscillator. r = preset divide ratio of binary 15-bit programmable refer- ence counter (1 to 32767). 13-bit b- counter 5-bit a- counter prescaler p/p + 1 from rf input stage modulus control n = bp + a load load to pfd figure 4. rf/if a and b counters rf/if counter the 15-bit rf/if r counter allows the input reference fre- quency to be divided down to product the input clock to the phase frequency detector (pfd). division ratios from 1 to 32767 are allowed.
rev. a adf4210/adf4211/adf4212/adf4213 C10C phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 5 is a simpli ed schematic. the pfd includes a xed-delay element that sets the width of the antibacklash pulse. this is typically 3 ns. this pulse ensures that there is no deadzone in the pfd transfer function and gives a consistent reference spur level. delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 r divider n divider cp output r divider n divider cp cpgnd v p figure 5. rf/if pfd simpli?ed schematic and timing (in lock) muxout and lock detect the output multiplexer on the adf421x family allows the user to access various internal points on the chip. the state of muxout is controlled by p3, p4, p11, and p12. see tables iii and v. figure 6 shows the muxout section in block dia- gram form. dv dd muxout dgnd if analog lock detect if r counter output if n counter output if/rf analog lock detect rf r counter output rf n counter output rf analog lock detect control mux digital lock detect figure 6. muxout circuit lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. it is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. it will stay set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k ? nominal. when lock has been detected, it is high with narrow low-going pulses. rf/if input shift register the adf421x family digital section includes a 24-bit input shift register, a 14-bit if r counter and a 18-bit if n counter, com- prising a 6-bit if a counter and a 12-bit if b counter. also present is a 14-bit rf r counter and an 18-bit rf n counter, comprising a 6-bit rf a counter and a 12-bit rf b counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb rst. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs db1, db0 as shown in the timing diagram of figure 1. the truth table for these bits is shown in table vi. table i shows a summary of how the latches are programmed. table i. c2, c1 truth table control bits c2 c1 data latch 0 0 if r counter 0 1 if ab counter (a and b) 1 0 rf r counter 1 1 rf ab counter (a and b)
rev. a adf4210/adf4211/adf4212/adf4213 C11C table ii. adf421x family latch summary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p1 p2 p3 p4 control bits 15-bit reference counter db21 if pd polarity three-state cp lock detect precision if f o if r counter latch db23 db22 if cp2 if cp1 if cp0 if cp current setting db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 a6 b12 p5 control bits 12-bit b counter db21 if n counter latch db23 db22 if prescaler if cp gain if power- down p6 p7 p8 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 6-bit a counter db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p9 p10 control bits 15-bit reference counter db21 rf pd polarity three-state cp rf lock detect rf f o rf r counter latch db23 db22 rf cp2 rf cp1 rf cp0 rf cp current setting p11 p12 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) a1 a2 a3 a4 a5 a6 b12 control bits 12-bit b counter db21 rf n counter latch db23 db22 rf prescaler rf cp gain rf power- down p17 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 p16 p15 p14 6-bit a counter r15 r15
rev. a adf4210/adf4211/adf4212/adf4213 C12C table iii. if r counter latch map r15 r14 r13 .......... r3 r2 r1 divide ratio 000..........0011 000..........0102 000..........0113 000..........1004 ................. ................. ................. 111..........100 32764 111..........101 32765 111..........110 32766 111..........111 32767 0 negative 1 positive 0000 logic low state 0001if analog lock detect 0010if r eference divider output 0011if n d ivider output 0100rf analog lock detect 0101 rf/if analog lock detect 0110if digital lock detect 0111 logic high state 1000rf reference divider output 1001rf n divider output 1010 three-state output 1011if counter reset 1100rf digital lock detect 1101 rf/if digital lock detect 1110rf counter reset 1111if and rf counter reset db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p1 p2 p3 p4 control bits 15-bit reference counter db21 if pd polarity three-state cp lock detect precision if f o if r counter latch db23 db22 if cp2 if cp1 if cp0 if cp current setting 0 normal 1 three-state p1 if pd polarity r15 p2 charge pump output p12 p11 from rf r latch p4 p3 muxout i cp (ma) if cp2 if cp1 if cp0 1.5k 2.7k 5.6k 0001.0880.625 0.294 0012.1761.25 0.588 0103.2641.875 0.882 0114.3522.5 1.176 1005.443.125 1.47 1016.5283.75 1.764 1107.6164.375 2.058 1118.7045.0 2.352
rev. a adf4210/adf4211/adf4212/adf4213 C13C table iv. if n counter latch map b12 b11 b10 b3 b2 b1 b counter divide ratio 000..........0113 000..........1004 ................. ................. ................. 1 1 1 .......... 1 0 0 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 0 0 .......... 0 0 4 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 n = bp + a, p is prescaler value set in the function latch. b must be greater than or equal to a. for contiguous values of n f ref , n min is (p 2 p). 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 0 disable 1 enable db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 a6 b12 p5 control bits 12-bit b counter db21 if n counter latch db23 db22 if prescaler if cp gain if power- down p6 p7 p8 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 6-bit a counter 0 disable 1 enable p6 p5 if prescaler p7 if power-down a6 a5 .......... a2 a1 a counter divide ratio p8 if cp gain
rev. a adf4210/adf4211/adf4212/adf4213 C14C table v. rf r latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p9 p10 control bits 15-bit reference counter db21 rf pd polarity three-state cp rf lock detect rf f o rf r counter latch db23 db22 rf cp2 rf cp1 rf cp0 rf cp current setting p11 p12 r15 r14 r13 .......... r3 r2 r1 divide ratio 000..........0011 000..........0102 000..........0113 000..........1004 ................. ................. ................. 1 1 1 .......... 1 0 0 32764 1 1 1 .......... 1 0 1 32765 1 1 1 .......... 1 1 0 32766 1 1 1 .......... 1 1 1 32767 0 negative 1 positive 0000 logic low state 0001if analog lock detect 0010if r eference divider output 0011if n d ivider output 0100rf analog lock detect 0101 rf/if analog lock detect 0110if digital lock detect 0111 logic high state 1000rf reference divider output 1001rf n divider output 1010 three-state output 1011if counter reset 1100rf digital lock detect 1101 rf/if digital lock detect 1110rf counter reset 1111if and rf counter reset 0 normal 1 three-state rf cp2 rf cp1 rf cp0 1.5k 2.7k 5.6k 0001.1250.625 0.301 0012.251.25 0.602 0103.3751.875 0.904 0 1 1 4.5 2.5 1.205 1005.6253.125 1.506 1016.753.75 1.808 1107. 7875 4.375 2.109 1 1 1 9.0 5.0 2.411 i cp (ma) r15 p9 rf pd polarity p10 charge pump output muxout p11 p4 p3 p12 from if r latch
rev. a adf4210/adf4211/adf4212/adf4213 C15C table vi. rf n counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) a1 a2 a3 a4 a5 a6 b12 control bits 12-bit b counter db21 rf n counter latch db23 db22 rf prescaler rf cp gain rf power- down p17 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 p16 p15 p14 6-bit a counter b12 b11 b10 b3 b2 b1 b counter divide ratio 000..........0113 000..........1004 ................. ................. ................. 111..........100 4092 111..........101 4093 111..........110 4094 111..........111 4095 a counter a6 a5 .......... a2 a1 divide ratio 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 0 0 .......... 0 0 4 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 n = bp + a, p is prescaler value set in the function latch. b must be greater than or equal to a. for contiguous values of n f ref , n min is (p 2 p). 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 0 disable 1 enable 0 disable 1 enable p15 p14 prescaler p16 rf power-down p17 rf cp gain
rev. a adf4210/adf4211/adf4212/adf4213 C16C program modes table iii and table v show how to set up the program modes in the adf421x family. the following should be noted: 1. if and rf analog lock detect indicate when the pll is in lock. when the loop is locked and either if or rf analog lock detect is selected, the muxout pin will show a logic high with narrow low-going pulses. when the if/rf analog lock detect is chosen, the locked condition is indicated only when both if and rf loops are locked. 2. the if counter reset mode resets the r and ab counters in the if section and also puts the if charge pump into three- state. the rf counter reset mode resets the r and ab counters in the rf section and also puts the rf charge pump into three-state. the if and rf counter reset mode does both of the above. upon removal of the reset bits, the ab counter resumes counting in close alignment with the r counter (maximum error is one prescaler output cycle). 3. the fastlock mode uses muxout to switch a second loop lter damping resistor to ground during fastlock operation. activation of fastlock occurs whenever rf cp gain in the rf reference counter is set to one. if power-down it is possible to program the adf421x family for either synchro- nous or asynchronous power-down on either the if or rf side. synchronous if power-down programming a 1 to p7 of the adf421x family will initiate a power-down. if p2 of the adf421x family has been set to 0 (normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three- state and then complete the power-down. asynchronous if power-down if p2 of the adf421x family has been set to 1 (three-state the if charge pump), and p7 is subsequently set to 1, an asyn- chronous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the 1 to the if power-down bit (p7). synchronous rf power-down programming a 1 to p16 of the adf421x family will initiate a power-down. if p10 of the adf421x family has been set to 0 (normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three-state and then complete the power-down. asynchronous rf power-down if p10 of the adf421x family has been set to 1 (three-state the rf charge pump), and p16 is subsequently set to 1, an asynchronous power-down is conducted. the device will go into power down on the rising edge of le, which latches the 1 to the rf power-down bit (p16). activation of either synchronous or asynchronous power-down forces the if/rf loop s r and ab dividers to their load state conditions and the if/rf input section is debiased to a high- impedance state. the ref in oscillator circuit is only disabled if both the if and rf power-downs are set. the input register and latches remain active and are capable of loading and latching data during all the power-down modes. the if/rf section of the devices will return to normal powered up operation immediately upon le latching a 0 to the appropriate pow er-down bit. if section programmable if reference (r) counter if control bits c2, c1 are 0, 0, the data is transferred from the input shift register to the 14-bit ifr counter. table iii shows the input shift register data format for the ifr counter and the divide ratios possible. if phase detector polarity p1 sets the if phase detector polarity. when the if vco char- acteristics are positive this should be set to 1. when they are negative it should be set to 0. see table iii. if charge pump three-state p2 puts the if charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. see table iii. if program modes table iii and table v show how to set up the program modes in the adf421x family. if charge pump currents ifcp2, ifcp1, ifcp0 program current setting for the if charge pump. see table iii. programmable if ab counter if control bits c2, c1 are 0, 1, the data in the input register is used to program the if ab counter. the n counter consists of a 6-bit swallow counter (a counter) and 12-bit programmable counter (b counter). table iv shows the input register data format for programming the if ab counter and the possible divide ratios. if prescaler value p5 and p6 in the if a, b counter latch sets the if prescaler value. see table iv. if power-down table iii and table v show the power-down bits in the adf421x family. if fastlock the if cp gain bit (p8) of the if n register in the adf421x family is the fastlock enable bit. only when this is 1 is if fastlock enabled. when fastlock is enabled, the if cp current is set to its maximum value. since the if cp gain bit is con- tained in the if n counter, only one write is needed to both program a new output frequency and also initiate fastlock. to come out of fastlock, the if cp gain bit on the if n register must be set to 0. see table iv. rf section programmable rf reference (r) counter if control bits c2, c1 are 1, 0, the data is transferred from the input shift register to the 14-bit rfr counter. table v shows the input shift register data format for the rfr counter and the possible divide ratios. rf phase detector polarity p9 sets the if phase detector polarity. when the rf vco characteristics are positive this should be set to 1. when they are negative it should be set to 0. see table v. rf charge pump three-state p10 puts the rf charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. see table v.
rev. a adf4210/adf4211/adf4212/adf4213 C17C rf program modes table iii and table v show how to set up the program modes in the adf421x family. rf charge pump currents rfcp2, rfcp1, rfcp0 program current setting for the rf charge pump. see table v. programmable rf n counter if control bits c2, c1 are 1, 1, the data in the input register is used to program the rf n (a + b) counter. the n counter consists of a 6-bit swallow counter (a counter) and 12-bit programmable counter (b counter). table iv shows the input register data format for programming the rf n counter and the possible divide ratios. rf prescaler value p14 and p15 in the rf a, b counter latch sets the rf pres- caler value. see table vi. rf power-down table iii and table v show the power-d own bits in the adf421x family. rf fastlock the rf cp gain bit (p17) of the rf n register in the adf421x family is the fastlock enable bit. only when this is 1 is if fastlock enabled. when fastlock is enabled, the rf cp current is set to its maximum value. also an extra loop lter damping resistor to ground is switched in using the fl o pin, thus com- pensating for the change in loop characteristics while in fastlock. since the rf cp gain bit is contained in the rf n counter, only one write is needed to both program a new output frequency and also initiate fastlock. to come out of fastlock, the rf cp gain bit on the rf n register must be set to 0. see table vi. applications section local oscillator for gsm handset receiver figure 7 shows the adf4210/adf4211/adf4212/adf4213 being used with a vco to produce the lo for a gsm base station transmitter. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ? . a typical gsm system would have a 13 mhz tcxo driving the reference input with- out any 50 ? termination. in order to have a channel spacing of 200 khz (the gsm standard), the reference input must be divided by 65, using the on-chip reference. wideband pll many of the wireless applications for synthesizers and vcos in plls are narrowband in nature. these applications include various wireless standards such as gsm, dsc1800, cdma, or wcdma. in each of these cases, the total tuning range for the local oscillator is less than 100 mhz. however, there are also wideband applications where the local oscillator could have up to an octave tuning range. for example, cable tv tuners have a total range of about 400 mhz. figure 8 shows an applica- tion where the adf4213 is used to control and program the micronetics m3500 1324. the loop lter was designed for an rf output of 2100 mhz, a loop bandwidth of 40 khz, a pfd frequency of 1 mhz, i cp of 10 ma (2.5 ma synthesizer i cp multiplied by the gain factor of 4), vco k d of 80 mhz/v (sen- sitivity of the m3500 1324 at an output of 2100 mhz) and a phase margin of 45 c. in narrowband applications, there is generally a small variation (less than 10%) in output frequency and also a small variation (typically < 10%) in vco sensitivity over the range. however, 100pf 51 v dd v p v dd 2v dd 1 adf4210/ adf4211/ adf4212/ adf4213 v p 1 5.6k 620pf 3.3k 8.2nf vco190- 902t v cc 18 100pf 18 18 rf out ref in muxout lock detect 100pf agnd if dgnd if rf in rf in b clk data le spi-compatible serial bus decoupling capacitors (22 f/10pf) on v dd , v p of the adf4211/adf4212/adf4213 and on v cc of the vcos have been omitted from the diagram to aid clarity. r set cp rf cp if 1.3nf 18 100pf 18 18 if out 100pf vco190- 540t v cc 3.3k 2.7k 100pf 51 1000pf 1000pf fref in 51 1.3nf 5.6k 620pf 8.2nf agnd rf dgnd rf v p v p 2 figure 7. gsm handset receiver local oscillator using the adf4210/adf4211/adf4212/adf4213
rev. a adf4210/adf4211/adf4212/adf4213 C18C v p v dd 2 adf4213 v p 2 3.9nf 470 130pf 20k 27nf m3500-1324 v cc 18 100pf 100pf 18 18 rf out 1000pf 1000pf 51 ref in muxout lock detect 51 100pf agnd if dgnd if rf in ce clk data le spi-compatible serial bus decoupling capacitors on v dd , v p of the adf4213, on v cc of the ad820 and on the v cc of the m3500-1324 have been omitted from the diagram to aid clarity. the if section of the circuit has also been omitted to simplify the schematic. r set cp rf 2.7k 12v v_tune gnd 20v 1k ad820 3k out fref in v dd v p 1 v dd 1 dgnd rf agnd rf figure 8. wideband pll circuit in wide-band applications both of these parameters have a much greater variation. in figure 8, for example, we have 25% and +30% variation in the rf output from the nominal 1.8 ghz. the sensitivity of the vco can vary from 130 mhz/v at 1900 mhz to 30 mhz/v at 2400 mhz. variations in these parameters will change the loop bandwidth. this in turn can affect st ability and lock time. by changing the programmable i cp , it is possible to obtain compensation for these varying loop condi tions and ensure that the loop is always operating close to optimal conditions. interfacing the adf4210/adf4211/adf4212/adf4213 family has a simple spi-compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of sclk will be transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz, or one update every 1.1 ms. this is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. aduc812 to adf421x family interface figure 9 shows the interface between the adf421x family and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf421x family needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. on rst applying power to the adf421x family, it needs four writes (one each to the r counter latch and the ab counter latch for both rf1 and rf2 sides) for the output to become active. when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed will be about 180 khz. sclock mosi i/o ports aduc812 sclk sdata le ce muxout (lock detect) adf4210/ adf4211/ adf4212/ adf4213 figure 9. aduc812 to adf421x family interface adsp-21xx to adf421x family interface figure 10 shows the interface between the adf421x family and the adsp-21xx digital signal processor. as previously discussed, the adf421x family needs a 24-bit serial word for each latch write. the easiest way to accomplish this, using the adsp-21xx family, is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. sclk dt i/o flags adsp-21xx sclk sdata le ce muxout (lock detect) adf4210/ adf4211/ adf4212/ adf4213 tfs figure 10. adsp-21xx to adf421x family interface
rev. a adf4210/adf4211/adf4212/adf4213 C19C pcb guidelines for chip scale package the lands on the chip scale package (cp-20), are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this will ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be clearance of at least 0.25 mm between the thermal pad and inner edges of the pad pattern. this will ensure that shorting is avoided. outline dimensions dimensions shown in inches and (mm). thin shrink small outline package (tssop) (ru-20) 20 11 10 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.260 (6.60) 0.252 (6.40) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 1 20 5 6 11 16 15 bottom view 10 0.080 (2.25) 0.083 (2.10) sq 0.077 (1.95) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.030 (0.75) 0.022 (0.60) 0.014 (0.50) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.080 (2.00) ref 0.010 (0.25) min 0.020 (0.50) bsc 12 max 0.008 (0.20) ref 0.031 (0.80) max 0.026 (0.65) nom 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) 0.035 (0.90) max 0.033 (0.85) nom seating plane controlling dimensions are in millimeters pin 1 indicator top view 0.148 (3.75) bsc sq 0.157 (4.0) bsc sq thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm grid pitch. the via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board pad to agnd.
rev. a C20C c01029C0C6/01(a) printed in u.s.a. adf4210/adf4211/adf4212/adf4213 revision history location page data sheet changed from rev. 0 to rev. a. changes to test conditions/comments section of specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edit to rf in and if in function text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pcb guidelines for chip scale package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 cp-20 package replaced by cp-20[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

▲Up To Search▲

Price & Availability of ADF4212BRU

	To Download ADF4212BRU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .